Design, Fabrication, Characterization And Packaging Of Silica-on-Silicon Based Triplexer

With the advent of high-bandwidth services such as IPTV and network, ADSL-based broadband access has been difficult to meet the demand of the users of high bandwidth, two-way transmission capability and security. Thus, the fiber-to-the-home (FTTH) emerged with its unique technical advantages.The essential component to deliver multi-play services in the time division multiplexing passive optical network (TDM-PON) system is triplexers.The development of low-cost triplexers using planar lightwave circuit (PLC) technology can offer advantages of easy fabrication and integration, cost efficient packaging, and mass scale production. In this thesis, we proposed and designed a compact triplexer based on the cascaded MMI with self-imaging principle. A compact triplexer is designed with three cascaded MMI sections. The total length of the MMI section does not need to be the common multiple of the coupling lengths. The device length of the present design is much shorter than that of a conventional design. The device can perform three-wavelength mux/demux function very well.Usually, a fiber array is first built by using V-grooves, fibers, lid glass and bonding materials. When a fiber array is directly butt-coupled to a photonic device, submicron alignment tolerances are required. Such alignment involves time-consuming signal monitoring, lowering the manufacturing efficiency. Furthermore, dicing and polishing processes are required to separate the chips into small pieces and obtain smooth waveguide facets. In this paper, we propose a simple method for fabricating the V-grooves integrated on device chips to avoid any further polishing process. To obtain the best precision through the V-grooves fabrication, we have utilized the photolithographic self-alignment principle for forming the etching mask for V-grooves during waveguide core etching. With such a process, the waveguides and the V-grooves can be fabricated without any lateral displacement (～0.2μm). The proposed method provides an efficient and low cost method for the package of PLCs.