Feasible Performance Modeling Of Analog Circuit Based On SVM

Nowadays, digital integrated circuits are designed primarily to take a top-down hierarchicaldesign methods. Because of the analog IC design’s complexity and its own limitations, itencountered many difficulties during the hierarchical design.However, it is the inevitable way toimprove the design methodology hours analog circuit design automation,and has made someprogress.During the process of the hierarchical design of analog circuits and systems, all the circuit cellsof every level need optimization and design,While the design of the basic unit circuit behavior layeris more critical step. In this step,the major factor needed to be ascertained is the design parametersof the performance of the circuit of the component units, but not the topological structure and thesize of all pipes. While, in order to meet each tube of the unit circuit can be saturated and the unitcircuit can comply with the design specification, the performance parameters of the circuit is not thefreely changed mathematical value of the variable. That is,to the definitized structure of a circuitunit, the performance parameters between the mutual often has constraints and satisfy certainconditions. Therefore, to achieve the behavioral analog circuit design, you must first make the basicunit of the constraint relationship between the various circuit performance parameters clear, namelythe performance of feasible domain model.The main work of this paper is the available study on analog circuit performance domainmodel. At present, the structure of a domain model analog circuit performance is more feasible andeffective method is the using of support vector machines to classification. Meanwhile, optimizecircuit performance goals to get long on performance parameters is the frontier in Pareto. As it is theperformance boundaries of the parameter space, it is also a description of the performance offeasible domain. In this paper, these two methods have been studied, written construction algorithmin MATLAB and use the tool of SVM, and then we used two CMOS op amp as an example, tobuild the model of the viable domain, and give the results, and based on the support vector feasibledomain model and a unified circuit Pareto frontier machines were compared and we found that ithas a good agreement between the two, which indicating the possible domain model structure iscorrect.