The Realization Of Multi-core DSP Parallel Scheduling Mechanism

In most recent years, multi-core DSP technology has been developing rapidly.Compared with the traditional multiple DSP architecture, multi-core DSP showsgreat advantages with lower power consumption, stronger processing ability andflexibility, and it has wide application prospect in the photoelectric measuring,image processing, intelligent traffic, automation and other fields. At the same time,the photoelectric theodolite image processing hardware platform transforms from aloosely coupled architecture of multiple DSP+FPGA to a tightly coupledarchitecture of multi-core DSP+FPGA. It requires the software programmingmodel changes to the directrion of multi-core DSP parallel scheduling. Meanwhile,the hardware platform shows several characteristics of miniaturization, highperformance, convenient programming techniques and flexible development. But itis still faced with many new chanllenges.The photoelectric theodolite image processing platform has upgraded from amultiple DSP chips schema to a multi-core DSP schema. The research work is basedon the system application requirements, which is put forward of the platform andwill maily be used in the “smart head” of the image qcquisiton. First it introducesthe technical kernels of TI multi-core DSP TMS320C6678, then combined with theactural needs of the “smart head” project, it solves the following technologiesrelated with multi-core DSP parallel mechanism.1. Design of CameraLink image data flow under the DSP+FPGA structure.These techniques are applied to the photoelectric theodolite image processingsystem. It can provide a complete hardware channel of the high-speed image datatransmission under the DSP+FPGA structure, which provides the hardwarefoundation of following research on the performance of multi-core DSP parallelmemory access and the parallel scheduling mechanism of multi-core DSP.2. Research on the performance of multi-core DSP parallel accessshared/external memory. In the multi-core DSP environment, there are severalmaster devices, the bandwidth of which prarallel memory access is crucial for thedesign of memory resources arrangement, software structure design of ourapplications. Drived by the application requirement, this paper analyzes the designprinciples of TMS320C6678multi-core DSP parallel access memory. 3. Analysis, comparison and verification of multi-core DSP parallel schedulingimplementation scheme. This paper compares the advantages and disadvantages ofthree kinds of prarallel scheduling scheme, namely data flow model, master-slavemodel and mixed models. Combined with typical examples of master-slave model, itproves the parallel processing ability of TMS320C6678multi-core DSP.