Design Of Programmable Frequency Transmitter Controller Synchronized By GPS

This thesis is based on the transmitter cooperation project of the laboratory and a army institute.As the confidentiality requirements of the armed forces,it’s uncleear about the application background and the main purpose of the transmitter. The transmitter is composed of a controller and a high-power pulse power. This thesis is about designing a GPS synchronized frequency programmable transmitter controller,which is used to control the high-power pulse power. The synchronization error is less than0.4μs,the output range of the frequency is between0.1Hz and20kHz. The error of special frequency points,which are given as41704.74Hz,744.727Hz,46.5455Hz, does not exceed0.01Hz.To achieve the functionality and performance indicators.Firstly,The design chooses a OCXO disciplined by GPS as a frequency standard source. Secondly,the design selects PLL (Phase Locked Loop) two inverter technology to generate the reference input frequency of the CPLD.Thirdly,the design uses ARM to provide frequency planning table.Finally, the design takes a CPLD to create the programmable frequency output. One step further, the design adopts TI’s CDCE913as Clock Synthesizer to create84.672512MHz as reference input frequencies. The design downloads frequency planning table created by VC6.0on PC through RS232and U disk into the FLASH of ARM.The design selects the logic language of Verilog to program the logic chip for getting the given frequency output.The maximum synchronization error detected by the Measurement and Testing Center is180ns,which is less than200ns.With the analysis of MATLAB mathematical tools and practical tests,In a series of special output frequencies, the maximum frequency error is generated at the frequency point of1489.45Hz,and the maximum error value is0.0045Hz,Which is less than0.01Hz.In summary,the controller meets the requirements of the project.