Hardware Design For Low Cost Wireless-Optical Access Node

Wireless optical broadband access network (WOBAN) provides a high-speed and low-cost solution for the telecom access network known as "last mile". WOBAN takes advantage of both Passive Optical Network (PON) and Wireless Mesh Network (WMN), such as high rate, large capacity, easy-to-access, low cost and so on. A hardware design for low cost wireless-optical access node is achieved. Besides, an efficient routing algorithm which can be implemented in WOBAN is proposed. Works of the thesis are summarized as follows:Firstly, an integrated routing algorithm based on Busacker-Gowen algorithm (BGR) is proposed. The concept of delay aware is introduced in BGR. Problem of maximize flow and minimize cost is then transformed to the question of maximize throughput and minimize average delay. The simulation results from Matlab show that, compare to MMHR, BGR can improve the throughput greatly at minimal delay cost.Secondly, a hardware design for low cost wireless-optical access node is proceeded. Wireless-optical access node can be divided into three parts: Optical access, Ethernet access, WiFi access. In optical access, the optical transceiver OPEP-33-A4Q1R is adopted to achieve photoelectric conversion, data flow to FPGA chip EP2C20through serdes chip SY87725L; In ethernet access, DM9000aep and RJ45is used for providing4ways of ethernet interface, and data are processed in EP2C20; In WiFi access, the UN5700WiFi module is employed, data are processed in ARM S3C2440and switched in the structure of FPGA+ARM. Cost factor is fully considered in the design. In order to reduce power consumption, the Surface Mounted Technology (SMT) is utilized.Thirdly, the hardware design for low cost wireless-optical access node is achieved, and the driver of certain module is compiled. Production specification of PCB are as below:4-layer, FR-4,35um/18um copper thickness, board dimension327.2mm x111.2mm x1.6mm, Surface draft immersion gold. Driver design including FPGA data interface for optical access and DM9000aep driver by using Quartus II and Verilog-HDL is completed. Linux driver of WiFi module is transplanted. At last we test and verify the whole design, provide an integral hardware and software platform for further study.