Research Of Automation Of RTL Design And Verification For SoC Reset Technology

SoC has been in the era of deep submicron, which is moving towards high integration and high performance. And it also brings great challenges to design and verification. With more and more peripherals supported in SoC, an effective management of each module reset becomes more difficult due to kinds of requirements from modules. A common reset model is presented in this paper based on the above challenges mentioned. In order to short the time for design and verification of RTL, they are implemented in an automatic way.To achieve a differentiated management of the various modules in SoC, a common reset model (CRM) is abstracted after analyzing the requirements of each module. This model bases on a specific reset method, i.e. reset synchronization that combines the advantages of synchronous reset and the advantages of asynchronous reset, and it is particularly applied to the modern SoC chip. In the process to ACRM, it designs the overall framework first, followed by the workflow for ACRM, and the automation for RTL design and verification are implemented in order according to this workflow.In order to improve the efficiency of the design of the front end, this paper also discusses how to automate the RTL design and verification of the above model mentioned (ACRM). The automation for CRM is determined by a meticulous research for ACRM including the analysis of necessity and feasibility, the demonstration of quality assurance and the trade-off between handwork and automation.Finally, it analyzes the result from several actual projects, and it also makes an assessment for ACRM. It proves the validity of the common reset model and evident advantages of automatic implementation, such as cost time, efficiency, maintainability and code coverage.