Research On FPGA Calculation Method Of Typical Matrix Decomposition

RUL (RUL, Remaining Useful Life) prediction algorithms of space platformshould be performed on low-power embedded hardware because of the space andweight limitatons of the aircrafts. The FPGA based hardware computing will be abetter option for this problem for its flexible structure and efficient customizedcalculation. As an vital branch of numerical computation field, matrix factorizationsare crucial methods for feature extraction and least squares problem solveing inRUL prediction algorithms. Hence the matrix decomposition research based onFPGA has both theoretical and practical meanings for the realization of rapid orreal-time RUL predicting of aircraft on embedded platforms.Therefore, this thesis mainly focus on research of relevant matrixdecomposition methods with FPGA on specific research background like QR, LUand optimized Cholesky decomposition which are all typically applied inengineering. Above all, this article mainly accomplished design of generalframework of matrix factorization. According to the need of design pattern of large-scale matrix factorization, we tried hierarchical storage method and optimizedcommunication bus protocol and realized design of matrix factorization frameworkbased on Xilinx FPGA. Then we discussed both custom computing mode andHardware-Software Co-design mode using QR decomposition as an example. Downto the details, we put forward such dividing method based on calculating intensivecode and settled crucial problem of hardware-software collaborative design. Afterthat, we adopted reasonably parallel computing and efficiently multiplex of on-chipmemory to realize a comprise between system resource and calculating efficiency.At last, we realize to optimize both Cholesky and LU decomposition throughanalysis of typical framework of matrix factorization and custom computing modewhich showes better performance compared to others. And we comprehended howto choose different matrix factorization algorithms in multifarious least squareproblems according to performance valuations of all kinds of matrix triangularfactorization with various coefficients of the equations.Moreover, the corresponding test results indicate that the implementation ofmatrix factorization based on FPGA is capable of fulfilling the actualrequirements of matrix factorization with a maximum of10000dimensions. At the same time, the implementation is more valuable in practical for its drasticallyimprovements of efficiency compared to PC platform under the same level ofdecomposition scale.