Realization Of FPGA-Based Low-Power/Real-Time Smart Camera Miniaturization And Application Of Binocular Vision

Driven by the blooming of Internet of Things and the internal need of Big Data, Smart Cameras, as basic nodes of the Visual Sensor Networks, have been displaying a high research and market value with the coming of the Smart Times. In this paper, the basic concept of Smart Cameras is introduced firstly. After that, four issues which need analyzing and handling carefully when designing Smart Cameras are proposed according to the nature of the independent embedded system and the feature of limited resources. With low power consumption and cost, high performance and flexibility as the design goals in our mind, a FPGA-based smart camera named Smart-Eyes is proposed then, while the four issues are discussed and handled throughout the whole design flow.At present, there are two versions of the Smart-Eyes.· One is the basic version Smart-Eyes (V1.0), which has a complete framework of smart camera and almost all the necessary functions such as acquisition, storage, processing, transmission and display of the video image in real-time. The image resolution is720x576and the frame rate is25fps. The DVI interface and the Ethernet interface are both available.· The other is the optimized version Smart-Eyes (V2.0), which reduces power consumption through miniaturization, improves flexibility by using hierarchical structure and implements a binocular stereo vision system to enhance intelligence. As shown in the simulation results, our binocular stereo matching algorithm’s average percent of bad pixels is about11.3%at the frame rate of60fps based on the Tsukuba dataset provided by Middlebury for test. It infers that we realize a real-time binocular stereo vision system with considerable accuracy at the expense of reasonable hardware resources and achieve a better trade-off among algorithm speed, matching accuracy and hardware resources.