Research On Hard Real-time Multi-core Architecture Based On Shared Sram Automotive Control Applications

With the continuous development of automotive electronics, theperformance and safety requirements of automotive are increasingly toimprove, leading to much more single ECU (electronic control unit)numbers in the vehicle, and complex interconnection and softwarearchitecture. Thus the stability and speed of cable communication meetgreat challenge. A huge number of ECUs, has led to increasingly error rateof communication, and it is the main case of accident. Single ECU is notfit for this situation, a lot of semiconductor company introduce multi-coreECU to the automotive sector.In automotive applications, multi-core ECU not only can effectivelyreduce power consumption, improve performance, but also significantlysimplifies board interconnection structure, reduce the ECU communicationerror occurrence rate. There is not much research on multi-core ECU.Because ECU is real-time system, WCET in this system should beconsidered as an important issue.This thesis first design and analysis one dual-core architecture, whichis fit for automotive safely application, and then researched on the methodshow to get the multi-core ECU’s WCET, through a large number ofbenchmark tests, which comes from M lardalen research center, to gain amuch more tight WCET, by comparison, the proposed method is moreeffective.