The Research And Fpga Implementation Of FEC Algorithms For10G-Epon System

10G-EPON stands for10Gbit/s Ethernet Passive Optical Network and is standardized by IEEE. With the capability of providing a compatible means to significantly upgrade access bandwidth to lOGbps,10G-EPON will be an economically feasible solution to enable next-generation network-based appli-cations. FEC allows a link to operate with a higher bit error rate at the receiver. Consequently, FEC effectively increases the optical link budget, which in turn allows increased distance or split ratios. FEC becomes increasingly important as bit rate increases. For this reason, FEC is mandatory in10G-EPON.The selected FEC code in10G-EPON is RS(255,223) code which can of-fer approximately7.2dB coding gain to reduce the bit error rate(BER) from1E-3to1E-12for correcting random errors. Most of the conventional RS codec-s are designed to process serial data and have low throughput. The scheme of multiplexing more than one conventional RS codec to deal with the high throughput of10G-EPON can yet be regarded as a feasible solution, but brings huge area complexity and high processing delay.In order to solve the above difficulties, this paper carried out the following work:1. We had made a study of the work mechanism of10G-EPON FEC and summarized the requirements which should be satisfied when designing RS codec for10G-EPON.2. To overcome the shortcomings that the conventional serial encoding cir-cuit has low processing capability but high latency, a novel parallel en-coding algorithm based on the conventional serial LFSR is proposed. The new parallel algorithm is designed by applying look-ahead recurrence to the equations that the serial encoding circuit meets. The overall encoder architecture for10G-EPON is proposed and implemented using FPGA.3. To solve the problem that existing decoding algorithms cannot finish de-coding procedure in the time of a FEC block, a reformulated ME algorith-m is proposed. The new decoding algorithm is transformed from the ME algorithm and can always finish at the end of a FEC block. The decoder architecture with fixed decoding iteration times and low area complexity is proposed.4. We had applied the above RS codec to an ONU demo system and carried out interoperability testing with an commercial OLT terminal; the experi-mental result shows that FEC can bring an coding gain of about5.4dB.