A Study On Parallel Dependence Relations Decomposition Of Programmable Logic Controller

Program Logic Controller is started from1969s, by virtue of its high reliability, long life, simpleness, easy to operate and a series of advantages.Which make it popularized in industry control fields.With the improvement of industral control and the scale of software in programmable logic controller expands rapidly, The PLC can’t meet all performance requirements of the actual application. Domestic and foreign scholars have started looking for a better implementation of PLC real time high speed method, which based on the FPGA parallel architecture of high-speed programmable controller.This research has become the hotspot in the field of industrial control. This paper established dependence relations among the rungs from the data and control aspects. And proposed a method of decomposing dependence relations,then used FPGA to implement high speed PLC.The work of this paper mainly includes the following aspects.Based on analysis of the way of work about traditional PLC, we proposed the whole design scheme of FPGA-based PLC, including hardware platform, software flow, LD-VHDL conversion and kinds of key technologies.Analyzed the language of LD, divide the dependences between rungs, and proposed the parallel dependency decomposition algorithm, to determine the parallel execution level, finally realized the concurrent execution of PLC programs. The method can effectively excavate the parallelism of LD, set up concurrent model, and resolve the problem of parallel compiler of PLC in the world. Finally builded the FPGA parallel architecture for programmable controller compiling method and theory.Builded the middle converted form (logic expression) between LD and VHDL, because logic expression is fitted to IEC61131-3standard and liable to be translated the target code. Meanwhile given the corresponding transform algorithm and examples, also given the transformation algorithms and exams of the Boolean, timer/counter and function block instruction logic expressions.Implemented the machnaism of the way of cycle scan execute, I/O mapping shield in PLC on FPGA.Constructed the FSM model to simulate the work way of PLC,and used changed control signal to strike the conversion of states,then achieved the scan way of implementing.Come up with the automatic generation algorithms from LD to VHDL.The LD instructions including Boolean logic, timer, counter, function. In order to prove the validity of PLC performance and control logic based FPGA, given the experiments of the printed stereogram texture of hard cutting. Finally give the compared results of implementation between FPGA-based PLC and traditional PLC. Realize the concurrently execute of rungs on FPGA.At present, traditional PLC has been well established. PLC parallel compilation system in this paper is just a beginning in the experimental platform. This paper will give a helpful theoretical exploration and try for getting mature products and the development of next-generation parallel PLC.