A High Speed Low Power Circuit Design For Driving Spatial Light Modulator

Thanks to the developing of micro-electroic technics, the characteristic frequency of transistor made by silicon is becoming more and more high, and the power supply becoming lower. This trend make sure the emergence of high-speed low-power integrate circuit. In2010, the processor i7, made by intel, can work at3GHz clock rate. However, the silicon technics has its own limitation, the Mobility and the Forbidden Band is very low. These limitation block the long-term use of silicon. In2003, Israel’s scientist develop a multiple quantum well spatial light modulator digital signal processor which made by GaAs/AlGaAs, Using optical methods to achieve the vector and matrix parallel computing. The processor can achieve8trillion times calculus per second, the same rate as a super computer.Multiple Quantum Well spatial light modulator is made by GaAs, it need other chip supply driving voltage when it working. It can modulate space lights at real-time, changing optical signal to electroic signal. It is the key device which constitute the real-time optical information processing, optical caculate and optical neural network. It can achieve high speed and complex operations such as matrix multiplication and division. The spatial light modulator based on multiple quantum well is less power consume and faster response than the traditional liquid crystal modulator. So in order to take the advantage of multiple quantum well spatial light modulator, we need to improve the speed of the driving circuit and lower the power consume.In this paper we discuss a high speed, low power, big array spatial light modulator base on chart0.35technics. The research, systemic survey, circuit and layout design. In order to make more use of the chip, we designed the chip can operate in two different modes. The test result show that the chip can worked well at the different mode. However the design does not fully consider some practical issues, Test results and design specifications has a little different, preliminary view that is the clock jitter of the FPGA or the simultaneously switching noise cause the problem. The next step is go on test the chip. At the same time, we began the multi-bit driving circuit design.