Design And Implemention Of The Interframe Prediction Coding Based On FPGA

In the video data, temporal redundancy between frames is much more than spatialredundancy and coding redundancy. And the motion estimation algorithm for compressingtemporal redundancy has a large proportion of the entire video data compression encodingsystem. Therefore, the better the performance of the motion estimation, the better the qualityof the video image compression coding and the real-time performance. In addition, FPGA asan integrated control chip of logic and storage resources has played an increasingly importantrole in the hardware implementation of the motion estimation with the continuousdevelopment of integrated circuit technology.The main research work:Firstly, the study concludes the development status of the interframe predictive codingalgorithm and the motion estimation algorithm, as well as the advantages and disadvantagesof video compression system with different hardware implementation. The research objectiveof FPGA design and implementation of interframe predictive coding is proposed in thisarticle. It gives the overall hardware block diagram system design and the module designflow block diagram.Secondly, it gives the design ideas and the choice of algorithms, including the acquisitionmethod of the target pixel,the sub-pixel interpolation method, motion estimation relatedtechnologies and inter prediction transform coding. It gives the specific hardware design andthe design work of the modularity of algorithms, including the luminance pixel acquisitionmodule, sub-pixel interpolation module, motion estimation module. And it gives thesequential circuits of the system based FPGA, including A/D circuits, memory design, URAT output.Finally, the design of the project on ISE is downloaded to the chip and the results showthat the brightness acquisition module can extract the gray data effectively, the motion vectorof the motion estimation module can be effectively outputted and be stored, the syetem powerconsumption is lower and the consumption of logic resources is less.In addition, this paper presents a new matching block size and search range. It isdesigned to try to achieve the optimal matching position of the entire pixel and sub-pixeladaptive search, and the calculation is greatly reduced.