Design And Optimization Of Low-power Application Specific Instruction Set Processor

ASIP (Application Specific Instruction Processor) is a new type processor in embedded applications. It is a kind of special processor designed for specific applications. By making trade off between speed, cost, power consumption and flexibility, the designers customize ASIP to meet the demand of many design goals.The design of ASIP has great research value in embedded application.This paper mainly introduces the ASIP design approach, which includes the design of structure and the design of instructions.By using the hearing aids algorithm of the WOLA and the WDRC, we design the speed of the hearing aids module, update the instruction, optimize the hardware structure and reduce the power consumption.The major research and design work in this paper is shown as follows.1) Based on the main structure of the processor, this paper make an analysis of the architecture of the hardware, and compare the differences of processors.2) introduce the instruction of the processor, including the way that how the processor works with the instruction.3) Introduce the exponent module and the logarithm module in the ASIP processor.4) emphases the design of the butterfly module5) Based on the analysis of the SRAM circuit, this paper proposes the whole introduction of the entire SRAM circuit.6) based on the ASIP processor,this paper proposed the loop buffering structure, which optimize the whole program memory, reduce the power consumption of the whole chip.This thesis illustrates the analysis and expatiation for whole hearing aids processor. he FPGA verification,ASIC design, post-layout results and chip test results are also shown.By using the loop buffering,the power consumption of ASIP can be reduced by20%, fulfilling the requirement of the low power memory. The die occupies1.33X1.23mm2, Chip test exhibits that the total power dissipation of functional module is only162μW/MHz at clock frequency of20MHz, feed to the demand of the low power.