Design And Hardware Implementation Of High Performance And Rate-Free QC-LDPC

Currently, QC-LDPC is hot in the research of communication theory, and it is widelyemployed in commercial products. Along with the development of communication qualityand storage capacity, it is no doubt that the need of QC-LDPC, more powerful in errorcorrection and simpler in hardware implementation, is urgent. However, the research aboutQC-LDPC code design and its hardware implementation are inadequate. In view of thissituation, this study proposes a set of QC-LDPC code design algorithm based on pioneeringresearch. Meanwhile, it presents the hardware implementation method of this kindQC-LDPC.In the code design algorithm, three useful techniques are utilized: at first, obtain gooddegree distribution pairs via modified density evolution algorithm; second, reduce thenumber of short circles in mother parity-check matrix by proposed PPF algorithm; at last,enlarge the ACE value of short circles and girth of parity-check matrix. Setting the samecode length and code rate, the simulation results demonstrate that the waterfall and errorfloor performance of proposed QC-LDPC is better than its counterparts designed by otheralgorithm.At the same time, QC-LDPC code with code length576and code rate1/2is chosen andits register transistor logic descriptions of encoder and decoder are implemented in Veriloghardware description language. The validation result on Xilinx’s Virtex II Pro illustrates thedesign is correct.Decoder needs too many storage units and spends too much time in decoding iteration,which results in comsuming large area and low throughput. So the future research shouldfocus on decreasing the number of storage units and enhancing decoder’s throughput.