A Study And Implementation Of FPGA Based Power Amplifier Linearization For WCDMA Repeater

In order to guarantee coverage, power amplifier is used to enlarge thetransmitting power in the communication systems. But nonlinear characteristicsof power amplifier can cause signal distortion and spectrum expansion, introducingadjacent channel interference and greatly reduce its efficiency. To solve this problem,the linearization of power amplifier characteristic has become one of research hotspots of mobile communication.Signal’s high Peak to Average Ratio (PAR) in WCDMA communication systemsis more likely to cause a decline in power amplifier performance. Crest FactorReduction (CFR) is one of the key technologies to effectively reduce the high PAR.And the Digital Pre-Distortion (DPD) technique can ameliorate the nonlinearcharacteristics of PA for improving the system efficiency.This dissertation focuses on linearization technique of PA. Firstly, nonlinearcharacteristics and linearization indicators, memory and memoryless model of poweramplifier are discussed. And then some related principle about the single PAR andseveral PAR reduction techniques are presented. Secondly the hardware structure andthe software general design of the whole system are discussed. The system will bedivided into two parts in this design. One part is the implementation of the DPD andCFR technology base on FPGA, which is the core linear technology with PA, anotheris the realization of control interface modules base on MCU and some preprocessingmodules base on FPGA. Thirdly, the linear system of PA will be built with the wholemodules ware discussed in previous, the finally experimental results have shown thatACPR improvement by the proposed system is better than20dB, and DPD cancompensate the nonlinear and memory effects of power amplifier, suppress thespectral regrowth.