The Research Of Hardware Implementation Of Neural Networks Based On FPGA

Modern engineering application develops in the direction of large-scale and complexity,meanwhile, the change of the environment makes the practical control system have theproblem of complexity, nonlinearity, time-varying, uncertainty and other problems.Therefore it’s necessary to consider the external environment, controlled object and controlsystem as a whole to analyze and design when designing the control system. Faced withthese control problems, methods based on traditional control theory are difficult to obtainideal controllers to meet the systems performance req uirements. The neural networks, withgood fault-tolerant ability, nonlinear mapping and self-learning capabilities, provide possiblesolutions for these control systems.Neural network, with its inherent parallel nature, is not suitable to realize inmicro-processor, however, FPGA is widely applied in the hardware realization of neuralnetwork, for its parallel nature, abundant embedded hardware core unit with multiplying andadding function, and memory resources. Based on FPGA as the hardware platform, hardwarerealization methods of neural networks are developed in the thesis. Hardware realization ofneural network nonlinear activation function and its derivative is one of the difficulties, ofwhich the commonly adopted methods are look-up table method, the piecewise linearapproximation, higher order polynomial approximation and the CORDIC algorithm. Thesemethods do not take into account the area (logical resources), real-time and accuracysimultaneously. In this thesis, table-driven linear interpolation method to calculate theactivation function and its derivative is adopted, which combines the look-up table and linearapproximation method, using less hardware resources to achieve high-precision activationfunction and its derivative approximation.Design the system by linking System Generator and ISE, first using System Generator togenerate fix-point simulation model, then compiling the fix-point model into HDL model,last, executing function simulation, synthesis, implementation and chip configuration in ISE.In this thesis, the activation function module, single neuron module and fix-structure neuralnetworks are implemented in the Xilinx Spartan-3E1600FPGA, and the reinforcement learning system, including quadruple frequency module of the pulse encoder, AD/DA controlmodule, are also designed.