Implementation Of Adaboost Algorithm On FPGA For License Plate Detection

License plate detection is a key step of the license plate recognition, the efficiency of license plate detection affect accuracy of character segmentation and character recognition in license plate recognition, but existing license plate detection based on software can not meet the real-time requirements.In this paper, for computationally intensive and slow speed, by analyzing the existing Adaboost algorithm, the rich logic resources and high speed of efficiency of FPGA are utilized to design a hardware detection architecture based on zoom scale scanning window, and detailed analysised this detection architecture. Completed haar features training, weak classifiers and strong classifier.System control modules also implemented, such as video image collection and VGA output, etc.multiple sets of images are simulated and analyzed on Altera DE2₇0FPGA development platform, experimental results show that, Adaboost plate detection algorithm with hardware architecture have the advantage of fast and efficiency detection.