Research And Implementation Of Mimo Systems In Parallel Spherical Decoding

With the rise of the research of the fourth generation mobile communications, multiple input multiple output (MIMO) technology has become a research hotspot. MIMO signal detection is one of the research focuses in MIMO technology, and sphere decoding algorithm can obtaine the BER performance close to maximum likelihood detection, which makes it the most promising MIMO detection algorithms.For the shortcomings of the SD algorithm that its computation complexity depending on SNR and channel conditions, a fixed-complexity sphere decoding algorithm (FSD) is studied, and an improved algorithm for hardware implementation is proposed in this paper.By improving the iterative calculation of channel preprocessing in FSD algorithm for single calculation, Computation is reduced to approximately1/3of the pre-improvement, when16QAM and64QAM modulation is adopted in the BER of10-5, the performance of the modified hard-output FSD(MFSD) algorithm was reduced by0.4and0.48dB than before the modification, the BER performance of the modified soft-output LFSD(MLFSD) algorithm was reduced by0.05and0.01dB than before the modification. By employing the simplified search branch configuration in the tree search process of MLFSD algorithm, making it easy for hardware implementation, the search branch number after simplified is only1/16of the origin, when16QAM and64QAM modulation is adopted in the BER of10-5, the performance of the simplified MLFSD algorithm was reduced by0.6and0.58dB than before the simplification.For the simplified MLFSD algorithm, its hardware architecture is designed and optimized from the two aspects of algorithm adjustment and hardware implementation, reducing hardware resource consumption under the premise of maintaining the same data throughput.For improved the channel preprocessing, its intermediate calculations can be provided to the Cholesky decomposition and zero-forcing equalizer module, reducing the hardware resources consumption of division, pseudo-inverse matrix and matrix multiplication.For the Cholesky decomposition module, by combining with tree search formula the root operation is eliminated.For tree search, a parallel structure is designed according to simplified search branch configuration, making the hardware architecture to support parallel data processing, by selecting different number of parallel branches corresponding to different modulation, a compromise can be achieved between the hardware resources and data throughput. The architecture of matrix inversion, matrix parallel multiplication and Cholesky decomposition in this paper also have a certain degree of reference.Finally, the hardware architecture of the MLFSD algorithm is implemented on Xilinx’s Virtex-7series FPGA chip XC7VX485T.By using model-based design methods in Simulink, the efficiency of the design and verification of HDL code is improved. when16QAM and64QAM modulation is adopted in the BER of10-4, the performance of the FPGA implementation of sphere decoder in this paper is decreased by0.7and0.65dB than its floating-point implementation, and the data throughput is up to1.08784Gbps, meeting the data throughput requirements of the standards of IMT-advanced.