Qc In Coherent Optical Communication - The Ldpc Code Performance Analysis And The Realization Of The Decoder

With the development of optical communication technology,100G and abovecoherent optical communication must use polarization-division multiplexing and highorder modulation, for example,100G optical fiber communication system is the mostwidely used PDM-DQPSK, and QAM etc.. While transmission rate enhance andmodulation order number increases, the communication system is more sensitive tonoise, such as additive white Gauss noise, phase noise and dispersion.LDPC code (low density parity check code) has become a research hotspot incommunication system FEC (FEC), optical fiber communication is not exceptionalalso. Compared with the traditional RS codes, LDPC code in optical fibercommunication using have better decoding performance, LDPC code is becoming anew generation of optical fiber communication in error correction coding. This papermainly studies the performance of LDPC codes in coherent optical fiber communication,LDPC codes generally refer to the binary LDPC code, and coherent opticalcommunication using high order modulation mode, which requires a mapping methodto make the binary code suitable for the high order modulation mode. This paperverified that as long as the decoding using the corresponding modulation LLRcalculation method, a binary LDPC code is also applicable to high order modulationmode, and different modulation mode can still maintain the same performance gain. Incoherent optical communication phase noise is an important factor that affects systemperformance, therefore the communication system requires the use of phase estimator toreduce the effect of phase noise. This paper studies phase noise on the LDPC decodingand its influence with the help of phase estimation, and proposed a modified LLR(logarithmic likelihood ratio information) method, this method can save someperformance loss. Dispersion must take into consideration in optical fibercommunication, this paper studies the telecommunication channel equalizer for LDPCdecoding effect, and analyzes the selection for the optimum parameters of equalizer.LDPC code excellent performance is largely due to the soft decoding, classical decoding algorithm of LDPC code contain BP algorithm and MIN-SUM algorithm.Considering the complexity of hardware implementation of LDPC code, this paperdesigns a kind of LDPC code decoder based on MIN-SUM algorithm, and uses Veriloglanguage to complete the logic implementation. The hardware architecture, the decoderuses the ping-pong operation, so that the utilization rate of hardware resource isincreased, at the same time using the the loop line storage for QC-LDPC code,improves the memory address decoding efficiency, in the process of data operationspipeline operation method are used to improve the decoding rate.