Can Be Automatically Generated Soc Development Of Eda Tools To Implement The System Bus

Interconnect bus is one of the most important components in SoC (System onChip) design. It connects all masters and slaves in system, organizes data transaction,and ensures the accuracy and latency of the data transaction. During the development ofSoC design, designer often needs to change the system architecture and topology ofinterconnect bus. To design a reusable interconnect switch bus, which can meet most ofthe requirements of different system architecture and different project, is an importantresearch topic in SoC design.This topic is based on the perl language and verilog RTL design, to develop a setof EDA tool for interconnect bus auto-generation. The main parts are:1．Analysis the standard spec of frequently used bus protocols, define thearchitecture of the system bus and data flow.2．Using perl-Gtk module, design a simple GUI (Graphic User Interface) for userto input the detail information of the masters and slaves, configure the topology ofinterconnect bus. Then user can use this tool to generate the RTL source code andverification environment of the interconnect bus.3．In original RTL source code, with “ifdef” code of verilog, user can use perlscript to extract the real RTL code for his configuration, and construct the system bus.Then, for different project, user just needs to input the data bus information inGUI, then the EDA tool can generate the RTL code for interconnect bus automatically.If user wants to change the bus architecture, user only needs to modify the configurationof interconnect bus. This can shorten much of the SoC development time, and ensurethe accuracy of system bus.