| With the rapid development of the new energy, high-efficient, long-life, low-powersupply become to be one of the most focus of attention. The primary side feedback AC/DCswitching power converter is used widely in the low-power switching power supply adaptapplications, because of its advantages of low cost, high efficiency, small size and so on.This thesis based on the control model of Pulse Frequency Modulation（PFM） designs aprimary side feedback switching power supply chip. This chip works in constant-current modeand constant-voltage mode to achieve constant current and constant voltage output. This Chipinclude bandgap reference, under-voltage lockout circuit, oscillator, error amplifier, lowdropout regulator, leading edge blanking modules and so on. The emphasis of this thesis isimproving the accuracy of output voltage and system anti-interference capability.The error amplifier is one of the core circuits in the control loop of switching power supply,its performance affects the stability and output accuracy of the entire system. This thesispresents a type of the error amplifier composed of small gain pathway which is rapidly and thelarge gain pathway which of be slowly, The gain of rapidly pathway is40,the gain of slowlypathway is400.When load changes rapidly, the rapidly pathway regulates the output voltageand keeps the rapidly response of the system; And till the system is close to stable, slowly pathvoltage will gradually replace the rapidly pathway and become the main rule, achieve high gainof the error operation amplifier. In theory, the error amplifier in this thesis achieves outputvoltage differs less than40mV from a lighter load to full load, while traditional error amplifierdiffers200mV,improves the accuracy of the system’s outputs.Traditionally, in the cycle which the “ON Time” of switch is long, wrong pre-shutdownwill be produced easily due to ESD and EFT interference after LEB time, and the switch has therisk of be bombed if there is a long time interval from this time to the normal logic shutdown.This thesis is to design a smart module to improve anti-interference capability of the system.The first plan is to regulate the LEB time according to the length of “ON time” of the switch.Because the reference voltageVcs_refof the primary peak current detector indirectly reflects the length of “ON time” of the switch, so we can adjust the time of the LEB according to themagnitude ofVcs_ref,which can reduce time from the end of the LEB time to the normalshutdown time, there will be little risk. The second plan is to get the latest “Off time” of switchdetermined by the time which is from open of switch to pre-shutdown of the switch,that is, theswitch will be turn off in time when the danger occurs.Finally， based on CSMC0.35μm BCD process, the chip was implemented. The area ofthe chip is0.9mm×1.35mm. The chip test results are: AC input voltage scope is90~300V,theconstant voltage error is less than5%,the error of constant current is less than10%,output rippleis less than160mV,efficiency of73%,The performance of EMI achieves to EN55022B standard,margin7.6db,anti-ESD capacity up to10KV,anti-EFT up to3.5KV,In addition, chips containssome protection: over-temperature protection, short-circuit protection and so on. The design ofthis paper can also provide some technical references. |
PDF Full Text Request