The Design And Research Of Digital Lock-in Amplifier Based On FPGA

The lock-in amplifier is a weak AC signal detection device, according to thecharacteristics of the detection that the measured signal and reference signal is related,while noise and reference signal is not related, it can significantly suppress noise andimprove the sensitivity and signal to noise ratio of the detection system. With thedevelopment of electronic technology, the lock-in amplifier basically goes throughthree stages of analog circuits, mixed analog and digital circuit, and all-digital circuits.Field Programmable Gate Array (FPGA) is very flexible, and able to easily modifythe design, which makes it very suitable for the study and design of digital lock-inamplifier. Due to the complexity of the design of the lock-in amplifier, and the needfor all aspects of technical experience, making that there is a certain distance betweenthe domestic lock-in amplifier and abroad, but if we can develop the special type ofdigital lock-in amplifier for specific requirements, it will greatly reduce the difficultyof the design. In this thesis, the digital lock-in amplifier is designed on the basis ofthis idea for the national “863” Project about infrared gas detection.First of all, study the basic idea of the lock-in amplifier, self-correlation functionand cross-correlation function, and compare self-correlation detection technologywith cross-correlation detection technology, as well as the analog demodulation anddigital demodulation technology of the signal. By comparing the self-correlationdetection with correlation detection technology, the latter has better noise immunity.Therefore, according to the cross-correlation detection theory, design an orthogonalvector digital lock-in amplifier.Secondly, because the signal is very weak which need to go through someprocessing before the cross-correlation detection. Therefore, we research and designthe detector bias circuit, two signal amplification circuits based on the OP07chip,dual feedback bandpass active filter circuit, and12-bits A/D converter circuit based on the AD9220chip.Then, as the core section of the paper, combine ALTERA DSP Builder designplatform with the Quartus II software, and make the design of the signal detector.(1),direct digital synthesis (DDS) technology has a high frequency resolution and a veryshort frequency conversion time, and can easily change the output signal amplitude,frequency and phase. Therefore, we design the orthogonal reference signal having thesame frequency with the measured signal by the DDS technology (frequency at10kHz).(2), design a12-bits×12-bits multiplier, in order to achieve the multiplicationof the measured signal and reference signal.(3), design a cutoff frequency of4kHz,64-order FIR low-pass filter for filtering the output signal of the multiplier.Finally, as the experimental section of the paper, after the graphical design andsimulation by using the DSP Builder design platform, generate hardware descriptionlanguage with Simulink, and download to the EP1C6Q240C8of ALTERA FPGA chipwith the Quartus II software. The detection results for the signals with frequency of10kHz and amplitude of20~100mV show that the measured output DC voltage isconsistent with the calculated value (theoretical value should be half the actualamplitude), the maximum error of single measurement value is less than5%, therelative error of the average is less than1%. This also indicates that the lock-inamplifier is reliable.