Characteristics Of Dislocations In Directionally Solidificated Multi-Crystalline Silicon Ingots

The usage of casting multi-crystalline silicon predominates in the whole photovoltaic industry, but the conversion efficiency of multi-crystalline silicon solar cell is always lower than mono-crystalline silicon solar cell. This is mainly because there are a lot of dislocations and other crystal defects in multi-crystalline silicon. We have researched the micro and macro-distribution of dislocations in directionally solidificated multi-crystalline silicon ingots and the effect of dislocations to electrical properties of crystalline silicon base on the method of dislocation etching and statistic calculation for dislocations in crystalline silicon. In addition, we have also done some preliminary research on the distribution characteristic of dislocations in directionally solidificated quasi-single crystal silicon material which is newly introduced by the industry. In the research of dislocation etching, we discovered the depth of the polishing corrosion is a decisive factor for the effect of dislocation etching, when the depth of polishing corrosion is more than19μm, the affect of damaged layer to dislocation can be ignored. In addition, when the depth of polishing corrosion is more than45μm, the observation plane will become flat. Through repeated experiments, we have built up a set of specifications of dislocation etching. Subsequent research results of dislocation characteristic show the distribution features of dislocations have various types in multi-crystalline silicon wafers which are from directionally solidificated multi-crystalline silicon ingots. Some grains have high dislocation density, but the dislocation density of neighbouring grains is very low. Some dislocation etching pits perpendicular to twin boundaries, others attaching to grain boundary. Dislocation density is lowest at the bottom of the whole multi-crystalline silicon ingot, and it increases gradually along the solidification direction. The maximum density appears at the top of the ingot, and it is4-5times as more as the lowest density. On the same horizontal cross-sectional of the silicon ingots, the dislocation density is almost in a same order of magnitude. The deviation of dislocation density is very small at the bottom cross-sectional, but sometimes there is a little deviation at the middle and top cross-sectional. The influence of dislocations to the electricity performance of silicon wafers is obvious, where there is low dislocation density; there is low minority carrier lifetime and resistivity. Conversely, there will be high minority carrier lifetime and resistivity. In quasi-single crystal silicon wafers, the border areas between single crystals and multi-crystals have the highest dislocation density. Now and then, there is low dislocation density in local multi-crystalline areas. The single crystal areas haven’t complete lattice structures; there is relatively high dislocation density in these areas. There even show sub-grain boundaries which are compose by reticular dislocations.