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GPS/Beidou Time Synchronization Device In Power System Based On FPGA

Posted on:2014-02-25Degree:MasterType:Thesis
Country:ChinaCandidate:L H YaoFull Text:PDF
GTID:2230330398460814Subject:Control Science and Engineering
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Power is a basic resource which is related to national economy and people’s livelihood, and is a main switch for social and economic operation. Therefore, it is particularly important to guarantee the safe and stable operation of the power system. In order to prevent and analyze the development process and reasons of the accidents, a comprehensively and accurately monitor for the running state of the modern power system that covers a wide area is needed. To achieve this goal, unified time information is required for the power system automation equipment, thereby the need for time synchronization device is extremely urgent.In this paper, the time synchronization device uses GPS/Beidou dual-mode timing and external IRIG-B code redundancy backup in order to ensure the reliability and stability of the clock signal source. In addition, modular building scheme is adopted, which makes it possible for the device to output the timing signal for a variety of types and interfaces in order to adapt different occasions and devices. The core idea for the time synchronization device designing is that, using the satellite time signal when it is available to tame the local clock and synchronously outputs high-precision time information, otherwise using the local clock to realize the automorphic functions to ensure the reliability of time synchronization in power system.Based on the analysis of the power system time synchronization method and punctuality technology at home and abroad, also according to the application requirements of the time synchronization device, we design the general framework scheme of the GPS/Beidou time synchronization device and analyze the working principle of each module briefly.To achieve high-precision punctuality is the core content of this thesis. In the project, we employ a phase-locked loop control principle to tame the local OCXO and accomplish the punctuality function on the basis of FPGA. DAPU Communication Technology Co., Ltd.023A-10.00MHz OCXO is selected as the local clock. Firstly, the local second pulse signal is obtained by using divide control of the local clock. Secondly, the deviation of the local1PPS and external1PPS is obtained by using the equivalent pulse counting time interval measurement method. Finally, the output frequency correction of the local oscillator is completed by using the PI controller. The master control unit of this system is TMS320F2812which is a DSP chip. We have designed the power supply circuit, the clock circuit, the reset circuit and the JTAG interface circuit. GPS M12T timing module and BD timing module used in the time synchronization device are introduced, and the function of each part of the signal output board and human-computer interaction module are briefly described. In terms of software implementation, the modular design concept is adopted to complete the design of the main program, satellite signal synchronization out-of-step judgment program, clock source selection program and crystal oscillator tame program.After all the work has done, we build up an experimental platform and conduct the system testing from two aspects of the punctual performance and output signals. The experimental results show that the GPS/Beidou time synchronization device is in accordance with the DL/T1100.1-2009Power System Time Synchronization System-Part1Technical Specifications and other related standards. The time synchronization device can be widely used in the power system.
Keywords/Search Tags:GPS/Beidou dual-mode timing, crystal oscillator tame, punctuality, timesynchronization
PDF Full Text Request
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