Research And Design Of Low Power Low Noise High Precision Instrumentation Amplifier For Implantable Neural Signal Recording

Recently, the neural signal recording technology is growing vigorously and pushing forward the development of neuroscience and neuroprosthetics, which offers hopes for patients.The analog frontend interface in the implantable extracellular recording SoC bridge the gap between neural signal and e digital processing unit. The instrumentation ampfier locates in its front and determines the resolution of the following analog-to-digital conversion. Thus, based on the research of instrumentation amplifiers, this thesis proposed and implemented a low voltage micropower instrumentation amplifier for cellular neural signal recording SOC, which is capable of processing both local potential field and action potential.The thesis is organized as follows. The first chapter is introduction. The characteristics of electrode and neural signal were discussed in the second and third chapters respectly. According to the input signal and frontend circumstance, the system requirements of the instrumentation amplifier was put forward in the forth chapter.In the fifth chapterthe design techniques of the low noise low offset amplifier was investigated and discussed in detail..And the design of a high performance instrumentation amplifier was proposed in the sixth chapter. In the design, the independently biased capacitive-feedback topology is applied to high-pass filtering of the electrode offset voltage (EOV), which reduces the capacitor area to 1% of the conventional topology. In addition, by removing the resistance driver from the structure, the power consumption is reduced.In design of the transconductance operational amplifier (OTA), by using auto-zeroing technique and ping-pong topology, the offset of theOTA is reduced downto microvolts. Moreover, chopper stabilization is adopted to treat the white noise folding arising from the sample-and-hold mechanism of the auto-zeroing. As results, the proposed 1V supply one-stage current-starving cascade OTA achieved 160dB DC gain and 2MHz GBW with 2uA current. Sincethe auto-zeroed input stage is embedded in the OTA without extra bias current and the common mode feedback circuits are realized by a continuous time two stage differential amplifier instead of resitive averager, the chip area and thermal noise is effectively reduced. D-flipflops and inverter lockers are applied in this work to eliminate the glitches in the control logic caused by circuits delay.This work is simulated and implemented in SMIC 0.18um CMOS process. The instrumentation amplifier achieves 40dB close-loop ac gain in the bandwidth of 0.1-10kHz with inaccuracy of 1.6% and 0.01% THD at 2.5kHz. The input referred noise is 36uVrms in the bandwidth of 0.1-10kHz. This chip generally achieves the performance specification in implantable neural recording.