The ASIC Implementation Of SoC Of Hardware Accelerator For Operating System Based Deep Sub-micron Process

In this paper, we make a deep research on the ASIC implementation of the SoC which focus on the hardware accelerator for real-time operating system based on the 32-bit open-source processor OR1200. The design of the FPGA prototype conversion method, flow of logic synthesis, formal verification and static timing analysis, the system layout, power network analysis and design, the clock tree design and physical verification methods were analyzed and discussed and completed the back-end work for the SoC system.The SoC system of Real-time operating system hardware accelerator, begin with wishbone bus interconnect specification integrates open source 32-bit microprocessor OR 1200, independent research and development of real-time operating system hardware accelerator RTA, the interface for chip NOR Flash, SDRAM controller, SD card interface, SPI Master controller, UART controller, AES encryption and decryption modules, network interface and GPIO controller.ASIC implementation process of the first complete FPGA-based SoC prototype optimization system, the use of two bus architecture, system architecture for the system from the low-power design a solution, as well as subsequent development to upgrade the system provides more Application expansion interface; in the back-end physical implementation, formal verification, simulation, static timing analysis complement each other to ensure the consistency of each stage of transformation; in the power network part of the proposed dual power and dual power ring to carry out the strategy section Chip the concrete implementation of the power network, avoiding the DRC in the physical verification checks on the width of the slot unauthorized repair, improve the stability of the system-chip power supply network.This chip produced with SMIC 0.18um 1P6M process,10 voltage 3.3V, the core voltage 1.8V, operating frequency 100MHz, about 1 million gates after physical synthesis, silicon area 2.5mmx5mm. It had been taped out from the SMIC successfully. QFP208 package for board level test, after the actual test, the whole SoC system can works well, in typical operation, the system power is about 219mw, achieved the expected goals.