Research On Technique Of Regular Expression Marching Based On FPGA

In recent years Regular expression is a hotspot in the string matching field due to its strong and flexible expression ability. A lot of network security systems based on the protocol identification, such as Intrusion Detection System(IDS), Content Filtering System and Firewall have used regular expression to describe their rules. As the key of the whole system, the designing of the matching engine has become the decisive factor of affecting system performance.In the traditional way, regular expression is software based. It works at serial model, which has a lower throughput, and take up a lot of CPU resources. With the growing network traffic, it is unable to meet the need of network security. Therefore, the thesis use the hardware to solve this problem of its low throughput. Considering the characteristics of the FPGA, the thesis implements regular expression marching engine on the FPGA.This thesis explains the characteristics and advantages of regular expression, and then discusses its two kinds of realized automation. Based on the NFA, it gives the detailed mapping circuits of a variety of meta characters, and optimizes the design by the way of giving a Sharing comparator. Through parallel processing and resource sharing of design, it's able to not only reduce the logic resources, but also increase the throughput greatly.The overall design adopts advanced hierarchy design idea to simply load corresponding top modules, no matter how the bottom modules are designed, when the rule library of regular expression needs to update. It is easy to upgrade library due to the repeatable programming ability of FPGA. The final design has been timing simulated and amounted to 8.7 Gbps matching performance on the VIRTEX-5, which could match one character in each cycle.