Research On Limit-Factors In IC Design-Tool Application

EDA-tool-based IC design works have become primer abilities for new designers with features such as cost-decreasing, time-to-market shorting and reliability enhancing.However, the negative defections of key known limit factors in EDA-tools will show that (1) genuine tools increase design costs, (2) HDL-running delays time-to-market, and (3) non-converging or not repeatable results shower the IC design engineers'passions.The two main objectives of the thesis: one is on limiting factors in EDA-tool applications with HSPICE and the other is for chaos analysis and control with tool of DC use. Both are based on our experimental designs (TSMC65nm).The four main contents of this paper include that (1) one problem is focus on HSPICE-based Convergence, another one is discovering and overcoming Chaos in DC design results; (2) to construct Linux servers environments for HSPICE or DC running; (3) to capture, analyze and build relations as Yi = f(Xs); and (4) to show diagnosis rules and solution methods for reducing effects about limit convergence and chaos.Conclusions A be one novel flow for pre-diagnoses on limit convergence (4-step); B be avoiding chaos with multi-run method (n>3). All above works are for EDA user future positive references.