Featureverilog And IPPL Development Methodology

To increase the reusability of IP softcore, it is always the case that IP softcore has plenty of configuration items and use conditional compilation (CC) directives to implement it. The usage of CC directives makes the code of IP softcore very complicate and hard to understand, which bring many problems to its maintainance and usage. In this thesis, we firstly propose the concept of IP softcore Product Line (IPPL). IPPL is the collection of IP softcores that are designed for a same project. We discuss the universal existence of IPPL. Then we disscuss the problems of Conditional Compilation used in IPPL development. At last, we introduce the Feature-Oriented Programming (FOP) to IPPL development. FOP is a new Software Product Line (SPL) programming paradigm in Software Engineering domain. We propose a Feature-Oriented IPPL development method and extend Verilog to support this method. We name the extened Verilog as FeatureVerilog. We implement a prototype compiler for FeatureVerilog and use it to implement the OpenRisc 1000 IPPL with our method. The comparision with existing Conditional Compilation implementation show our advantages.