Fabrication, Characterization And Circuit Design Of Organic Thin-Film Transistors

Organic thin-film transistors (organic TFTs) have attracted wide attentions from academia and industries, due to their promising applications in flexible and large-area electronics. However, to achieve the system integration based on organic TFTs for practical applications, significant efforts are required to push the progress in all levels of organic electronics research including materials, devices and circuit design. For this purpose, this thesis covers the following aspects:Firstly, newly synthesized organic semiconductors BDNT (benzo[1,2-b:4,5-b'] di(naphtha [2,3-d] thiophene)) and DTBT series (based on thieno[3,2-b][1] benzothiophene cores) were characterized. The devices fabricated with the octadecyltrichlorosilane (OTS) modified SiO2 as the gate insulator layer on silicon substrates present excellent performance. The highest mobility can reach 1.75 cm2/Vs for BDNT and 0.5 cm2/Vs for DTBTE. By using OTS treated polymer dielectrics polymethylsilsesquioxane (PMSQ) and polyacrylonitrile (PAN) as the gate insulator, the organic TFTs using the two organic semiconductor materials were fabricated on polyethylene terephthalate (PET) substrates, with the mobilities of most devices based on the two organic semiconductor materials in the range of 0.15 cm2/Vs～0.5cm2/Vs. Flexible organic TFT devices were further investigated. The pentacene organic TFTs were fabricated based on the polystyrene (PS) modified PAN and PAN-only dielectrics. The results showed that the PS modification layer can greatly improve the device performance with the mobility being increased from 0.013 cm2/Vs to 0.55 cm2/Vs. The organic TFT devices based on PS/PAN dielectrics also performed well under the ON-OFF switching durability and cyclic mechanical bending tests, which shows the great potential for flexible electronics applications. With the light assisted charge trapping, multi-bit memory effects were observed for the same structure devices. The related physical mechanisms were discussed in details.Finally, to address the circuit design for organic TFTs, the noise margin of p-type-only inverters were investigated, and a simple noise margin model was derived to build the relationship between the noise margin and device and design parameters. For both Zero-VGS load inverters and Dual-Vth type inverters, the obtained noise margin results with the model agreed well with those obtained by circuit simulations with HSPICE circuit simulators.