Research And Implementation Of Elliptic Curve Cryptography Over GF(2~233 )

Elliptic curve cryptosystem ECC is an efficient substitution of the mainstream public key encryption system RSA nowadays. It can provide the same safety of RSA just by using a smaller key.ECC now is the highest security per bit of public key cryptosystem. Since the key length is small, so the system need lower power consumption, smaller transmission band- width and less storage space , but the system has higher computing speed and safety.The theory of ECC cryptosystem is complex, ECC need a large amou- nt of calculation, and there are many kinds of parameters that need to be selected,so we need to simple this problem with hardware design .The goal of This paper is to implement the ECC binary field of hardware with high speed. In order to show the advantages of hardware design: high speed and safety, this paper choose the KOBLITZ K-233 curve as the elliptic curve. Our system use the fixed parameters, and use trinomial as the irreducible polynomial, beside this,we have done much algorithm level optimization, and we finally achieve our goal:realize high speed calculation with small area .We firstly research the algorithm of all level of the ECC point scalar multiplication.then we select the algorithms that suitable for hardware imp- lementation.Finally we do some further optimization efforts to these select- ed algorithms; especially for the design and implementation of the speed bottleneck -- modular multiplication, we use serial parallel hybrid multip- lication.We firstly use KOA method to ruduce the number of the needed multiplication, then we realize a 64bit multiplier with parallel implem- entation method,and finally our realization of a pair of 233bit multiplica- tion only need 9 clock.when do each multiple,we will simultaneously do a portion of the reduction, and finally we just need one more clock to complete 465bit reduction; for scalar multiplication ,this paper proposal an improved parallel implementation of scalar multiplica- tion.We combine a point addition algorithm and a point double algorithm to just one unique algorithm,then we add one more multiple and use parallel computing met- hod, the time required for a point addition reduced from 80 clocks to 37 clocks; for modular inverse operation, we don't use Euclidean algorithm- m,but by reusing the modular multiplication and modular square to realize it.Based on the ECC binary field algorithm, we use VLSI to implemente our ECC IP. By using hierarchical top-down design method, we firstly def- ine the structure of the system, then we do function module division, final- ly we use Verilog hardware description language to realize it. Based on the SMIC 0.18 m CMOS Technology Library, running in the 80MHZ, our IP scalar is 91K Gate. The IP is more fast compared with other designs.