.3 D-ic Thermal Analysis Algorithm Research

3-D ICs is a new technology for achieving high density, low power and cost effective designs. As a result of dies deing stacked over each other, the technology poses a challenge of heat flow and temperature management. We propose an algorithm for performing the steady-state thermal analysis in 3-D multi-chip design. By using finite element method (FEM) as the basic simulation engine, we construct a global heat conduction equation of the whole 3-D multi-layer chips. To simplifier the calculation, the Cholesky factor are applied to the matrix of each component chip, which makes the whole thermal analysis equation be solved more efficiently by using the preconditioned conjugate gradient (PCCG) method. The proposed algorithm saves more than 90% of the iterations in conjugate gradient calculation and leads to a quicker coverage of the whole steady-state thermal analysis in 3-D multi-chip design. A die level thermal analysis tool which can analyze a stacked die configuration, modeling boundary conditions and fit into existing SoC design flows is the need of hour for 3-D IC designers. We propose an accurate yet efficient algorithm for performing the steady-state thermal analysis in stacked 3-D-chip designs, which meets the requirement exactly, is introduced. We present a flow for 3-D thermal analysis design and also present the results of experiments don to validate the flow. The finite element method (FEM) is used to implement the basic simulation engine. We create the package model of stacked 3-D-chip design with the minimal boundary. Present 3-D-chip design flows handle each component chip individually, but it is hard to get package model of each component. This New flow has better accuracy for thermal analysis of stacked chip and easy package model.