IP Design For USB2.0 Host/Device Controller And OTG Research

Integrating a large number of general interfaces for high-speed communication with peripheral or PC host is an elementary requirement of SoC. Because of simple architecture, low cost and plug-and-play support, USB is becoming one of the most popular interfaces. The new specification of USB2.0 has raised the data speed from 12Mbps to 480Mbps, fulfilling application of high-quality video data transfer and high-quanity data sampling. USB OTG is a new supplement to the USB2.0 that augments the capability of USB device by adding host functionality and communicating with other peripheral without PC host. This thesis focuses on IP design for USB2.0 host/device controller integrating physical circuit and research of USB OTG supplement, in consideration of strict realtime performance and resource limitation.After investigation of nowadays design technology, this thesis first gets a solution of hardware/software partitioning. From references to the OSI network communication model, a new layered architecture of host/device controller was developed from the traditional host controller architecture. Then deep analysis of the optimized structure was made in view of data flow, sharing resources and OTG implementation. By adding host/device functionality control logic in different layers, the system can be run under the management of host or device, which meets the definition of OTG dual role peripheral. Another unit is used to config the controller and neogiate with other OTG peripheral. According to the data transformation, detailed hardware blocks were devided and the key modules of them were optimized. In the bottom layer, an embedded physical circuit was discussed, which contains a high-speed data path and an analog transceiver.From the research into the host/device controller, the thesis proposes the following innovations and improvement: a new host/device controller architecture was obtained from the traditional host controller, and the new structure has an excellent result of sharing resources; to reduce the task of CPU, we design a DMA master to manage the on-chip data transfer, which uses split transaction to improve the efficiency of on-chip bus; in the physical layer, we bring a novel data recovery circuit to receive the serial data, that is the oversampling data recovery algorithm based on data edge information and sliding window. We design the 5 times oversampling circuit in the case of full-speed and 8 phases oversampling circuit in the case of high-speed, which increases both phase and frequency deviation tolerance. Moreover, verification of the USB2.0 host/device controller was made on the simulation platform—32bit RISC CPU based SoC.