Design And FPGA Implementation Of Synchronous Pll In Doubly-Fed Wind Power Converter

With the development of the global economy, the problems such as energy shortage and environment deterioration are getting worse. Many countries use renewable energy sources such as wind and solar energy as main measures to face up to the challenges of climate change and energy shortage. In recent years, power electronics technology is developing rapidly, and VSCF doubly-fed generators are also widely used in megawatts wind turbines generating system.This paper discusses the working principle, basic structure and mathematical model of the doubly-fed wind power converter; introduces the working principle of nets side and rotor side PWM converters; studies the design of controller in dual PWM converter; and derives the calculation formula of adjustment parameters in the controlling system. In order to gain good performance in the stability of dc-link voltage and controllability of the reactive power absorbed from the grid, double closed-loop structure that including inner current loop and outer voltage loop is adopted to control grid side converter. Correspondingly, in order to decouple the power generated by the machine and track the maximum wind power, double closed-loop structure including inner current loop and outer power loop is applied to control rotor side converter.In circumstances such as the voltage of the three-phase power grid is unbalanced or changed, PLL synchronization is particularly important in the grid converter. And the quality of phase lock loop is directly related to the performance of the converter system and the stability of operation. The paper studies the three-phase PLL based on the vector control. According to the coordinate transform principle, through the process from three-phase static coordinate system to two-phase static coordinate system, and then to two-phase rotation coordinate system. This completes the phase detecting functions of phase locked loop, and sampling the angle value of input three-phase voltage. Using PI control principle, realize the loop filter, set parameters according to actual conditions. Adopt accumulator principle to realize the numerically-controlled oscillation function and get the output angle value. Compare the value with the sampling angle value, we can find the three-phase phase locked loop can rapidly and accurately synchronize with the phase, frequency and amplitude of the three-phase input voltage.This paper completes a three-phase phase-lock loop design based on FPGA using Verilog language. First modular design the three-phase phase lock loop, which realizes functions of the phase discriminator, loop filter and NCO. With the top connections finished, the whole three-phase PLL design has completed. What's more, through the idea of pipeline, this paper studies an improved method of CORDIC algorithm which is faster and of higher precision than the traditional method.As a conclusion, in simulation environment of Modelsim, under the conditions such as the three-phase voltage balanced and unbalanced, or containing harmonic three-phase voltages, phase mutation and frequency mutation, simulate the three-phase phase lock loop designed in this paper. Analyzing the simulation results, we can find the proposed the three-phase PLL can satisfy the synchronization requirements of the system, and the stability and feasibility of the design are proved.