The Growth Of Self-organization. Palladium Nanocrystals Its Charge Storage Effect

With the development of semiconductor technology and downscaling of the device feature size, the conventional poly-silicon floating gate flash memories are facing a severe challenge that scaling of the tunneling oxide thickness will degenerate retention characteristics. Embedded nonvolatile flash memory devices based on discrete charge storages have been considered as one of the most promising candidates due to their improved retention characteristics in the case of a thinner tunneling layer, and faster program/erase (P/E) speed under lower operating voltages. Therefore, the fabrication process of Pd nanocrystals and its electrical characteristics as the charge-trapping center are presented in this thesis and the involved physical mechanisms are also discussed. The details include the following sections:(1) The formation of Pd nanocrystals on Al2O3 layer has been investigated by rapid thermal annealing (RTA) of sputtered Pd film. Firstly, the influence of various factors on the deposition rate of the initial Pd film has been studied, and the ideal depostition conditions have thus been achieved. Subsequently, the thesis has investigated comprehensively the influence of RTA temperature, annealing time, and RTA ramp rate on the growth of Pd nanocrystals. The results show that Pd nanocrystals are prone to be formed under conditions such as:magnetron sputtering target power of 10W, an Ar flow rate of 45sccm, a deposition time of 230s. Furthermore, the size of the resulting Pd nanocrystals increases and the nanocrystal density decreases with increasing the annealing temperature. The optimized annealing conditions are as follows:an annealing temperature of 850℃, an annealing time of 15 s, and a RTA ramp rate of 20℃/s. Accordingly, Pd nanocrystals with an average diameter of 10nm, and a particle density of 4×1011 cm-2 have been obtained. In addition, the growth of Pd nanocrystals on the conventional SiO2 film has also been investigated. It is shown that the process parameters such as target power of 10 W, an Ar flow rate of 45 sccm, a deposition time of 400 s, an annealing temperature of 750℃, an annealing time of 15 s, and a RTA ramp rate of 20℃/s can result in the Pd nanocrystals with an average diameter of 12 nm, and a density of 1.5×1011 cm-2.(2) Pd nanocrystals embedded in TiO2 high-k dielectrics have been prepared by reactive co-sputtering and RTA technique. The PdTiO films are firstly deposited by reactive co-sputtering in a plasma mixture of O2 and Ar, and then treated by rapid thermal annealing (RTA) at high temperatures in N2. As a result, the Pd nanocrystals are formed spontaneously embedded in titanium oxide by means of decomposition of Pd oxides and subsequent growth of Pd nuclei. The influence of Pd/Ti power ratio and RTA process on the formation process, the nanostructure and chemical composition of Pd nanocrystals have been investigated by the method of XRD, EDS, HRTEM, and XPS. The experimental results indicate that the TiPdO film with a high content of Pd is inclined to produce big nanocrystals. Furthermore, the higher the RTA temperature, the bigger the Pd nanocrystals become. In addition, our analyses of the x-ray photoelectron spectroscopy spectra reveal that PdO, PdO2, Ti2O3, and TiO2 coexist in the as-deposited film, and the RTA at 600℃leads to decomposition of the entire PdO2 and partial PdO, together with the growth of Pd nanocrystals. At the same time, the released oxygen oxidizes fully Ti2O3 into TiO2 during the decomposition. As the RTA temperature is increased up to 900℃, more and more PdO is decomposed and the Pd nanocrystals become bigger and bigger.(3) The MOS capacitors with Pd nanocrystals embedded in TiO2 film as the charge trapping layer has been fabricated, together with the ALD Al2O3 layer as the tunneling and blocking layers, and metal Pd as the electrode. The electrical measurement results show that Pd nanocrystals embedded in TiO2 film as the charge trapping layer result in good memory effect. When the sweep voltage range is±3 V, a memory window of 0.5 V can be observed. And the amount of the flatband voltage shift (ΔVFB) increases further with enlarging sweep voltage range and comes to about 8.2 V at±9 V. It is interesting to find that the memory window (i.e.,ΔVFB) increases abruptly from 0.5 to 3.1 V with raising the sweep voltage range from±3 V to±5 V. What's more, with reference to the forward sweep, the resulting VFB shifts distinctly toward a negative bias with increasing the gate sweeping voltage and no saturation of hole-trapping is found. As far as the backward C-V sweep, it is found that the resulting VFB shift obviously in the direction of the positive bias with increasing the sweep voltage and the saturation is also found. In other word, the resulting VFB shifts obviously in the direction of the positive bias with increasing the sweep voltage when the sweep voltage≤7V. However, when the sweep voltage≥9V, it shifts hardly, which indicates the saturation of electrons-charging. This is because the charges injection under low voltage is dominated by direct tunneling mechanism and F-N tunneling mechanism under high voltage. As far as the holes, however, the valence band offset of Pd and the controlling oxide is so large that F-N tunneling for holes though the controlling oxide to the electrode is unlikely to occur, so direct tunneling still dominates. It is also observed that when the stress voltage is equal to+9 V, the pulse width of 10ns could result a VFB shift of～2 V. When the pulse width is kept at 10ms, a stress voltage of+7 V could result in a VFB shift of～2 V. Finally, the maximum effective injected charge density is calculated to be about 8×1011 cm-2. Meanwhile, the basic process of the charge injection occurs in the initial stage, and the effective charge injection rate is about 6×1012 cm-2μs-1 in the case of 10-8 s, indicating a great potential for this memory structure.