I2c Bus Design And Realization Of The Soc System

I2C bus is widely used in the digital system because of simple interface, expedient using, low power design, and very good expansibility. Verilog HDL is considered as a core of digital system design and a key hardware description language to implement the digital system.This project modeling an I2C bus communication system based on Verilog HDL. At first the thesis deeply research I2C bus specification,then briefly introduce several common design environment and the design method,as well as design flow.In this foundation,I2C bus controller design scheme,operational principle of the timingstate,the realize of verilog HDL and the timing simulation under Xilinx is particularly introduced.The system uses a top-down design methodology and the structure-describing style of Verilog language,it is divided into several small module. All necessary modules which in order to implement the communication system are designed in this project. Then join the entire modules to implement the communication using the I2C protocol and UART protocol. Implement the basic function of the I2C bus communication system.