Virtual Mimo Channel Estimation Technology Research

MIMO technique can greatly increase capacity of wireless communication system by exploring spatial diversity. However, it is very difficult to implement multiple antenna more and more miniatured mobile terminals. Thus virtual MIMO (VMIMO) technique has been proposed to collect neighbours'antenna to form a Virtual Antenna Array (VAA). Alike traditional MIMO system, estimation status of MIMO subchannels of VMIMO system is still a most important step and much more challenging. This dissertation mainly focuses on the research of channel estimation of OFDM based multihop virtual MIMO system (VMIMO-OFDM). Main contributions of this dissertation are as follow:1. Following the two-hop relay selection method of the multi-hop virtual MIMO system developed by our project group, the dissertation proposes channel estimation protocol and method of VMIMO-OFDM system, which is based on the channel training using grouped pilots that are orthogonal among their owner, or participating nodes. When channel training nodes in the upperstream cluster are selected, the selected nodes sound the channel with training symbols on its subcarrier set, and the downstream nodes can sample the channels and obtain the channel response on all subcarriers by interpolation. The abovementiond protocol includes two main stages, one is to select the nodes which would take part in the channel estimation, and the other is the channel estimation process. During the first step, node selection and pilot group assignation are performed in distributed fashion and all nerghbor nodes obtain the unique solltion. The mechanisim has been implemented in MATLAB and tested.2. To further implement the above method in FPGA based board, the dissertation has setup a channel estimation verification platform under the Simulink cooperated with SystemGenerator developed by Xilinx for algorithm-level simulation. Furthermore, the verification platform is transformed to the ISE project in VHDL for delay and wave-level simulation in ModeSim. By using the same test file as that in algorithm-level simulation, the FPGA circuit parameters are optimized. When developing the implementation and verification platform, multiple signal selector is used in stead of the division operation of the channel estimation module to save FPGA resource. Both algorithm- and wave-level simulation are testified, and the optimized FPGA design is downloaded to FPGA to finish the design.