Digital Tv Receiver Signal Preprocessing And Synchronization Technology And Its Vlsi Implementation

The development of digital technology has brought a new revolution in television broadcasting. The digital TV (DTV) technology can be divided into three classes, satellite, terrestrial and cable. Cable DTV brings high-performance and high-efficiency transmission, while satellite and terrestrial DTV achieves the 3A (anytime, anywhere, anyhow) goal. But it also brings new challenges on related fields.With the development of wireless communication and VLSI technology, mobile DTV terminal are achieved. There are many DTV standards that are suitable for mobile DTV. In this thesis, China Mobile Multimedia Broadcasting (CMMB) and DVB-S2 are taken as examples. Although there are many studies on DTV receivers, improvement on performance are still required and some of them are not flexible enough to be transplanted to other systems. It is one of the goals that design a universal platform which can be transplanted from one receiver to another. That demands all the design flexible and reconfigurable enough.In this thesis, some classical algorithms are adopted and improved to apply in VLSI. Improvement on performance is also considered, as well as the tradeoff between performance and complexity. Much effort is put on the study of VLSI architecture with low-complexity, flexibility and reconfiguration. A compromise algorithm of I/Q imbalance elimination with low complexity and high performance is proposed. A coherent channel interference (CCI) filter with accurate detection and narrow-stop-band solution is also presented. The tradeoff among performance, complexity and speed of architectures is discussed. Optimum architectures of adjacent channel interference (ACI) filter and direct digital frequency synthesis (DDFS) with low complexity, reconfiguration and flexibility are proposed at the end of each section.The main work of this thesis includes:1. Investigating the background of DTV broadcasting and the DTV standards of difference countries. The advantages, development and future application of DTV receivers are presented. In this thesis, CMMB and DVB-S2 receivers are taken as representations, but the algorithms and architectures are flexible enough to reuse in other receivers.2. Analyzing the wireless communication link and Building the simulation model for satellite communication channel and terrestrial communication channel. Studying CMMB and DVB-S2 standards and building the transmitter models. Introduction on the devices of DTV receiver, including the principle of receiving antenna, tuner, A/D and demodulator is also presented.3. Research on the algorithms of signal pre-processing and synchronization in time domain, including direct current (DC) bias elimination, I/Q imbalance elimination, DDFS, ACI elimination, CCI elimination, sampling frequency & phase recovery and time error detector (TED). The algorithms are simplified to make them suitable for VLSI implementation.4. VLSI architectures of previous algorithms are discussed. These architectures are improved according to multiplexing and system requirements. Optimum architecture of I/Q imbalance eliminator with low complexity and sufficient performance are proposed. Three architectures of DDFS are presented. The application of these architectures in different systems is discussed, too. The application and architectures of ACI are also discussed in this thesis. A novel architecture of CCI filter is proposed too. A low-complexity and high-performance anti-aliasing filter is specially designed for DVB-S2 and other symbol rate adaptive receivers. A novel symbol synchronization algorithm with higher performance is redesigned for CMMB system.5. The previous algorithms can be implemented in DTV receivers without any change in architecture. But in practical, requirement of some receivers is quite different from that of others. That requires redesign or designing new modules to meet the requirement. Therefore the issue of building a practical signal synchronization sub-system of CMMB and DVB-S2 is put forward. The design reuse and redesign issues in practical systems are discussed respectively. The test platforms for these two systems are given, and the test results of FPGA and chip are presented as well.6. On the basis of this discussion, a universal sub-system of signal pre-processing and synchronization in time domain for DTV receivers is presented at the end of this thesis. In case that someone can benefit from this platform. This universal sub-system can be reused in other DTV systems, or embedded in receivers that support several DTV standards.Finally, the work of this thesis and future development are concluded. The simulation result and test result indicates that the proposed sub-system of signal pre-processing and synchronization has low complexity and high performance. The performance of overall system is much better. These demodulators can be applied in actual handheld terminal and vehicle equipment.