Bit-plane Coding In Jpeg2000 And Fpga Implementation

In image processing, image compression technology is essential for the storage and transmission of large amounts of data. The still image compression standard JPEG2000 is much better than JPEG in coding efficiency and the restoration of image quality. JPEG2000 still image compression will certainly dominate the field. However, the complex coding algorithm makes JPEG2000 difficult to meet real-time requirements, in particular, as the bottleneck of the whole encoder, Bit plane coding part has large computation and urgently needs dedicated hardware to realize. Therefore, it is important to study bit plane coding algorithm in JPEG2000 and its implementation with FPGA.Bit plane coding is used to encode those code block datas quantified after DWT, and output the context and the decision. Based on the research and improvement of bit plane coding, the algorithm, multi-word parallel bit plane coding algorithm based on a single mobile window, was proposed, and the software simulation of the algorithm were given in this paper. Afterwards, the hardware implementation of bit plane coding technique in the JPEG2000 standard was studied, and the specific VLSI architecture was given to realize the three coding channel in bit plane coding (cleanup coding pass, significance refinement coding pass, magnitude refinement coding pass) and the four basic coding methods (zero coding, sign coding, magnitude refinement coding, run length coding), and the corresponding module was programed with Verilog HDL. Finally, simulation and synthesis of the bit plane coding system was given, the hardware design of high-speed bit-plane encoder was confirmed correct and feasible.In the high-speed bit-plane encoder design, the entire run length coding was processed into a look-up table to improve the coding efficiency and simplify the circuit structure. Continuous sliding of 4×3 sliding window and continuous coding were realized by inserting Zeroes in edge. Performance analysis and experimental results show that the proposed VLSI architecture can more effectively reduce the cost of hardware. The multi-word parallel architecture greatly improves the system throughput and data processing speed, and it can meet the general requirements of real-time. The bit-plane encoder could complete real-time encoding of code block datas, in the frequency of 175MHz, which can be used as a separate IP core in EG2000 image coding chip.