The Frequency Domain Channel Estimation Algorithm And Vlsi Implementation, Based On Pilot

Digital television technology is bringing up a new industry revolution worldwide. As one of the most important application,transmission of digital TV to handheld receivers such as mobile telephones and PDAs,are known as the newest and most popular media.Now the related specification or standards for terrestrial mobile multimedia broadcasting are as below:DVB-H,which is proposed by ETSI,T-DMB, which is proposed by Korea and CMMB,which is proposed by China.In most wireless transmission environments,a wideband radio channel is time-variant,frequency-selective and noisy.So channel estimator and equalizer are very important.For the mobile terminal,how to compensate for the performance degradation induced by channel interference,while achieve low complexity and low power,have became rather difficult and critical.In this thesis we are targeting at the pilot based channel estimation and equalization on frequency domain.According to the principle of OFDM,and take the DVB-H standard as background,we analyzed all kinds of technology about channel estimation and equalization carefully.These are the key to digital terrestrial television broadcasting.Firstly,according to the analysis of wireless channel,a channel model for simulation is given.Based on the principle of the modulator and demodulator for DVB-H system,the main technology of channel estimation and equalization on frequency domain is developed.Secondly,a brief overview of the pilot-based OFDM on the background of DVB-H is given.Based on the various channel models,a self-select algorithm,in which the interpolation of the channel,including one order linear interpolation,two order linear interpolations,and frequency domain Wiener interpolation with time domain linear interpolation,can be used according to the channel conditions. Equalization and interpolation is used to the same symbol,and the effect of phase noise and Doppler frequency are also considered.Computational simulation results show that the proposed scheme has little BER loss in different kinds of channel models,and this method is preferable tradeoff between performance and complexity.Finally,on the basis of aforementioned algorithms,an optimized VLSI architecture for channel estimation and equalization is proposed.On detailed analysis of the VLSI architecture,data-path and signal processing flow,as well as module reuse information is illustrated.Some critical sub modules,such as equalization and filter for channel impulse response are optimized.Then the VLSI implementation results are presented.A general verification platform for DVB-H system is introduced and testing the above design.The results show that the proposed algorithms and VLSI structure achieve the design requirements and has promising application value.ASIC backend design is given in the end of this paper.