The Eeprom Embedded In The Soc And Application Design

As VLSI technology development, chip design has entered the nanotechnology era. Advanced process makes it possible to integrate the processor, memory, analog circuits, interface logic and even radio frequency circuit on a large scale chip to form a System-on-Chip SoC. In the SoC design process, in order to complete the design and improve system reliability within limited time. The traditional RTL synthesis design is difficult to achieve the purpose of reuse, and the IP reuse in the SoC design turn the circuit design into system design.Non-volatile memory IP reuse has become an important part of today's SoC system solutions. The IP reuse can greatly shorten the market cycle, better use of existing technology and reduce costs. Aimed at the demand of embedded memory in SoC system, the dissertation made a research in the eEEPROM IP's embed and verification in SoC system, the main work includes the following aspects:1. According to the design requirements, the IP hard core of Aplus was used, which includes 8k×14bit Flash and 128×8bit EEPROM, and then analysed the IP's interface and timing.2. Based on multi-mode access technology, the key circuits of eEEPROM in IAP and ICSP accese mode were designed,including buffer circuits, bus-compatible circuits and multi-mode access control circuits. Designed the workflow of eEEPROM in IAP and ICSP access mode.3. Designed the interface circuits of eEEPROM IP's enable signals, including program, read, all erase and single-byte erase. Constructed HSIM+NC-Verilog co-simulation platform, and finished simulation and verification of entire circuit. The IP could accomplish eEEPROM's functions and meet the design requirements. Designed layout of eEEPROM and run DRC and LVS, and then tested the chip's functions.4. Took the application of eEEPROM as an example, briefly introduced the operation of EEPROM, which verified the correction of eEEPROM.In the process of design, various software simulation methods and hardware test methods were applied to test eEEPROM's program, read, all erase and single-byte erase functions. The SMIC 0.35um 2P3M CMOS process was employed to simulate and verify the eEEPROM's functions.