Airport Runway Identification Algorithm And Implementation

Runway detection is a key technique during the UAV landing image navigation, which contribute greatly to promoting the development of navigation technique and reducing accidents during landing. In this thesis, in order to position the runway precisely during the UAV landing aiming at ensuring landing safety, taking some military airfield runway image as the object of study, runway recognition algorithm based on the monocular vision has been studied and partial hardware platform design as well as the algorithm in the hardware platform transplant has been completed.Navigation system guide the UAV to its landing aera, then starts the machine vision to recognize the mian airport runway and obtains the UAV landing location parameter to control the UAV landing. Starting with digital image pretreatment, the image segmentation and image refinement are studied emphatically. In straight line extraction, the shortcoming of traditional Hough transformation merely to be able to extract the straight line but not to be able to determine the straight line vertex is overcomed. False vertex processing is introduced. Mathematical model is established based on structure characteristic of some military airport. The main airport runway identification and determination of its parameters have been completed. And validity of the algorithm is confrimed through the simulation.In the design of concrete hardware platform, The FPGA peripheral circuit's design, the DSP EMIF interface circuit's design, power circuit's design and input circuit's design have been completed. The electric circuit connection schematic is given in this thesis.The design and debug of the program is the focus of this thesis,which is mainly divided into FPGA and DSP two parts.The design of FPGA program mainly includes the design of image processing module, the SDRAM controller module as well as the control module. Image processing module completes the opreation of color image to gray image and image filtering. SDRAM controller module completes the storation of processed data to external memory. And the control module completes the communication control between FPGA and DSP. Function simulation and timing simulation have been completed by using ACTIVE HDL. And real-time confirmation is done by using Signal TapII. The debugging result of hardware platform indicates the validity and the rationality of the system design. The debugging result of FPGA and DSP program indicates that the recognition algorith running in hardware platform has the feasibility and correctness.