Sha-1 Coprocessor For The Trusted Computing Platform Research And Implementation,

In this information society, the people's lives are changing with the development and application of information technology. Information becomes important property which is exploring to much more threats. Undoubtedly, a trusted computing environment to guarantee the privacy, integrity, reality and reliability of information has been one of urgent needs of the business and public.Trusted computing environment is established by enhancing the security of current architecture of PC terminals to secure the whole system. The main idea of it is to introduce a trusted architecture on PC hardware platform to improve the security of it. The core of this technology is a trusted chip called TPM(Trusted Platform Module) which is a SOC contains cipher computing component and memory. RSA and SHA-1 which are two primary algorithms in cryptology are used in cipher computing component of TPM.SHA-1 is a Hash algorithm widely used worldwide and has been de facto standard in information security industry, which brought forward by NIST and NSA together. For an initial message with a maximum less than 264 bits, the SHA-1 produces a 160-bit message digest. Any change to the initial message will result in a different message digest. It is computationally infeasible to find a message which corresponds to a given message digest, or to find two different messages which produce the same message digest.Currently SHA-1 in many applications is mainly software-based implementation. But Sofeware-based SHA-1 cannot meet the higher speed demand brought by the exponential increasing information to be propected. Hardware-based implementation as an effective way to improve SHA-1 computing speed is an inevitable technology trend. So, the coding algorithm and its implementation design are the focus of this thesis.This paper goes through SHA-1 itself at the beginning and then focuses on pipeline technology and parallel computing architecture, both of which are main way to improve computing efficiency of SHA-1.But when applied into trusted chip, They cannot suit well system demand of the chip.So this paper presents a new loop iterative unrolling hardware architecture to implement SHA-1.The main idea of this architecture is to combine two consecutive iterative steps into one step and reduce hash operations from originally 80 steps to 40steps. Meanwhile, this architecture multiplexes logical function in each round thanks to their similarity and optimizes critical path using CLA. To facilitate porting to other security chip, this architecture and WISHBONE bus interface are encapsulated as a module, so that it can be easily used as an IP soft core.