The Wcdma Downlink Receiver Hardware Implementation Of Technological Research And The Base Station Transmitter Module

WCDMA is one of the main standards in the third generation of cellular communication system. WCDMA can support data services with at most 2Mbps speed and allow many kinds of speed services multiplexing. So the design of receiver is very important.In the first part of this thesis, the performance of chip equalizer is studied. Conventional RAKE receiver can not eliminate the multiple access interference. Chip equalizer can decrease the multiple path interference by restoring the orthogonality of the transmitted sequences. Then the interference cancellation is studied. Because the transmitting sequences of pilot channel are same in different frames, pilot channel can be rebuilt. The interference caused by dedicated channel can also be rebuilt by using the results of decoder, which is called iterative interference cancellation. The performances of two methods of cancellation are analyzed.According to the research about chip equalizer and interference cancellation, the hardware design is studied. A method of reducing the complexity of calculation and storage is presented.The second part of this thesis shows the hardware implementation of base station transmitting module. The problem about division of module, arrangement of timing signals and interface of CPU are discussed. At last the thesis presents the consumption of hardware resource and the result of testing.