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Design And Implementation Of Decoding Dvb-s2 System,

Posted on:2007-08-29Degree:MasterType:Thesis
Country:ChinaCandidate:W C YaoFull Text:PDF
GTID:2208360182990420Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
Digital video broadcasting for satellite service has been greatly developed during the recent years. DVB-S, introduced as a standard in 1994, is now used by most satellite operators worldwide for television and data broadcasting services. Since 1997, digital satellite transmission technology has evolved, especially in channel coding schemes combined with higher order modulation, variable coding and modulation (VCM), adaptive coding and modulation (ACM), and the flexibility to cope with more input data formats. DVB-S2 was introduced in 2004, which is characterized by a flexible input stream adapter, a powerful FEC system based on LDPC codes concatenated with BCH codes, and a wide range of code rates and etc.Based on DVB-S2, the thesis presents the hardware implementation of the outer BCH decoder using Verilog. After studying on the decoding algorithm and analyzing its complexity, the thesis makes an improvement in the implementation by applying a more parallel-focused design. Simulation on C platform is done and Verilog coding verified on FPGA is finished as well. All the modules of the BCH decoder are illuminated in details with a deep analysis of its performance.The first chapter gives an overview of DVB-S2 and its main differences from DVB-S. In chapter 2, a typical channel model for satellite application is presented with a basic study on its channel capacity. Chapter 3 concentrates on the decoding algorithm of BCH and its complexity. In chapter 4, the problem of finding the minimum distance in large linear codes like BCH is discussed, and the decoder's general performance is analyzed theoretically. The hardware implementation is presented in chapter 5, carrying out a highly-parallel design. The decoders' performance is illustrated. Chapter 6 makes a summary of the whole thesis.The main contribution of this thesis is presenting a design of BCH decoder with high parallelization in DVB-S2. Meanwhile, a theoretic study on the minimum distance of linear codes is made with a probabilistic algorithm given.
Keywords/Search Tags:DVB-S2, BCH decoder, Minimum Distance, Syndrome, Error locator polynomials, Chien Search, Parallelization
PDF Full Text Request
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