Digital Voice Tdd Walkie-talkie The Design And Realization

Today, the resources of frequency bandwidth become more and more exiguous because of the high-speed development. People have been doing the best to compress the transmission channel frequency bandwidth or to reduce channel data rates .The design of 4Kb/s data rates, which the paper has depicted, has its applied value. It can be applied to many domains such as wireless communications, VoIP, secure communications.This paper accomplishes the hardware design and implementation of a speech compression system and a TDD (Time Division Duplex) system. The system adopts an advanced specific speech compression chip based on AMBE algorithm. It can achieve high compression rate at 4 Kb/s .The system first performs A/D conversion on analog speech input to obtain PCM signal and the PCM signal was encoded by the main compression chip. A FPGA is used as controller, performing the necessary processing such as eliminating the system head of the encoded data frame, adding channel frame head and storing the speech data into FIFO. At the receiving end, a inverse process is performed to restore the analog speech signal. This paper first introduces some typical compression algorithms. Then, some analysis of the structure and principles of the system are given, placing emphasis on introducing the speech compression chip. With these done, the control programme is compiled and simulated. Moreover, some improvements are given. Finally, the hardware debug is achieved and the analysis of conclusion also is given.