Hardware Design And FPGA Implementation Of Random Demodulator For Line Detection

Spectrum detection technology plays a decisive role in radio astronomy observations. Some important features of astronomical, such as running track, density of the total particle and age, can be found by the spectrum. The frequencies of the spectrums which are radiated by the molecules corresponding to these features are very high, the order of magnitude is GHz. The astronomical observation backends based on traditional high-speed signal sampling have many limitations, the requirements of astronomers for observing more spectrums and observing simultaneously multipler otational transitions of molecules whose frequency are far are not met.Radio astronomy signal is sparse in the frequency domain, Compressed Sensing theory is proposed for signal which is sparse in one domain. The CS theory can solve major problems that high sampling rate ADC and Large-capacity data storage in traditional sampling by achieving High-frequency signal. The systems for Signal acquisition based on CS theory sample and compress the signal at the same time. It samples at low rate, gets less information in CS. The original sparse signal will be reconstructed by solving optimization problem. Random demodulator, modulated wideband converter and multi-coset sampling are proposed to make CS practical.This paper analyses and studies signal sampling and reconstruction theory of random demodulator. The hardware circuit is designed On the basis of the simulation results. Sampling and reconstruction of random demodulator are implemented with FPGA. Firstly, the fundamental of CS is elaborated. Three core problems and three patterns of CS are introduced. Secondly, random demodulator is analyzed deeply and simulated in Algorithm level. Finally, random demodulator is implemented on hardware, The hardware circuit includes the following parts:In the part of pretreatmenting signal, the circuit board is designed and made by selecting chips carefully and simulating each module to make sure it is correct; The ADC and SDRAM are controlled by FPGA to sample signal and cache data; The sparse vector of original signal is reconstructed by the OMP algorithm which is improved before implementing. The system is optimization designed by parallel implementation, resource multiplexing and avoiding square root calculations to improve computing speed and reduce the complexity of the hardware:The simulation of random demodulator verified the correctness of the system. It make full use of the advantage of the FPGA parallel computing to sample signal which is sparse in the frequency domain at a relatively low sampling rate and observe it’s spectrum. The experimental results show that, the system realizes compressive sampling, it completes spectrum detection for the signal whose highest frequency is80MHz by lower sampling rate40MHz.