Design Of Real - Time Clock Chip Based On High Precision A / D Converter

In this thesis, an RTC(Real-Time-Clock) chip is designed.It counts seconds, minutes, hours, days of the week,date of the month, months and years until9999.It can compensate leap-year automatically,and select between12-hour and24-hour clock display.It includes two alarms that can realize different alarm functions with seconds,minutes,hours,week,and date. And it has a programmable square wave module,which can output16kind of different square waves, as32.768kHz,16.384kHz...1Hz.The interface circuit of the chip is2-wire I2C bus.I2C bus can communicate at400kbps in fast speed mode,which meets the speed requirements of RTC absolutely,and it saves hardware source compared with parallel bus because it needs just2wires.The frequency of a crystal oscillator varies with the environment temperature.To stabilize the frequency, the temperature-compensated system of the oscillator needs to get the environment temperature information by temperature sensor,and then convert the analog temperature signal into digital data by an analog-to-digital(ADC) converter,and then look up the storage according to the temperature information to get the frequency compensation value at the current temperature,and finally complete the frequency compensation of the oscillator.Considering the crystal oscillator varies with the environment temperature just slightly and after the contrast of various ADCs,I adopt a successive approximation(SAR) ADC with moderate-rate,high-resolution,low power dissipation.The SAR-ADC designed in this thesis is12bits and2.18Ksps.Its sampling clock is32.768KHz from the crystal oscillator. The ADC consists of a sample and hold circuit,a comparator,a charge distribution digital-to-analog converter(DAC),and a12-bit successive approximation register circuit.In traditional temperature-compensated system,we usually convert the voltage from OV to1.5V by a12-bit ADC,but in this paper we just use a12-bit ADC to convert the voltage from0.9V to1.5V,so the ADC designed in this thesis has higher resolution.This design is carried out using top-down method.The Verilog HDL codes of RTC and PC bus have been simulated under the QuartusII software environment,and verified by Altera corporation’s FPGA.we drew the schematics of ADC,and simulated the ADC circuits using the Cadence software.