.10 Mhz, ~ 1ghz Small Step Frequency Source Design

This dissertation introduces a realizable scheme of 10MHz ~ 1GHz small step frequency source, which implement by DDS directly incentives PLL and down-conversion. The system is divided into two paths, one path generates a signal at 2.4GHz single frequency as the mixer's LO that generated by the PLL chip phase-locked. Another path generates a sweep signal between 2.41GHz ~ 3.4GHz, and its step is 1Hz. DDS is used to generates a 24.1MHz ~ 34MHz sweep signal, and its step is 0.01Hz.The input signal of DDS is generated by a phase-locked loop, the output signal of DDS is used by other PLL chip's as its referenced input signal, the PLL multiply the frequency by 100 times, the output signal of the PLL is used as the mixer's RF signal.Firstly, the paper gives a brief look in the basic idea of frequency synthesis, including PLL frequency synthesis and direct digital frequency synthesis technology. Then it analyzes advantages and disadvantages of several DDS+PLL frequency synthesis technologies. Combined with the requirements of the task targets, we determine the implement after analyzing the scheme's feasibility. The following contents are the design of each module's circuit, which describes the key technology of each module circuit design and the configuration of each chip's registers. Finally, the debug of each module is discussed in details, and the test results are given.After repeated circuit debugging and optimization, we finally get the following results: Output frequency is 10MHz-1GHz. The phase noise is better than -67.82dBc/@ 10kHz. The spurious rejection is better than 31.41dBc, and the output power range is from -8.01dBm to -10.02 dBm.